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Microservices Journal: Article

Tilera Begins Unveiling Its Gen3 Many-Core Chips

Tilera segments the market, optimizing chips by where they’re bound

Tilera, the many-core processor start-up, is drumming up business for its third-generation hydra-headed chips, expecting to have samples ready this summer, a tad late but, hey, nobody ever said this stuff was easy.

The company's 40nm Tile-Gx line is meant to be available with 16, 36, 64 and 100 64-bit RISC cores on a single die.

Tilera segments the market, optimizing chips by where they're bound.

Marketing VP Troy Bailey says that "Networking applications need maximum throughput and lots of I/O in a dense form factor, while the cloud computing market wants the best performance-per-watt in order to save energy and cooling costs. And multimedia calls for a balance of high-performance signal processing and I/O. We have created three different processor series to accommodate these varying requirements."

The Gx 8000s Tilera's promoting right now are targeted at demanding networking applications that require high bandwidth and a lot of throughput so they include what the company calls a "rich set" of input/output ports, packet processing and network acceleration features.

They're also supposed to be optimized for intrusion prevention and detection (IPS/IDS), unified threat management (UTM), firewall, virtual private network (VPN), WAN optimizer, network monitoring, network forensics, test equipment, data leakage protection (DLP) and e-Discovery.

Bailey says the part "delivers all the critical needs for a broad range of networking applications."

Tilera means to have a Tile-Gx 5000 series optimized for multimedia applications and a Tile-Gx 3000 series for cloud server applications. It won't be ready to talk about them until later this quarter.

Once it drops that veil it will start sampling all three of its 36-core devices in July and all three of its 16-core versions in August. The 64- and 100-core parts will sample at the end of the year. Tilera had hoped to start sampling by the end of Q1. Its target before that was Q4.

The company is fab-less so Taiwan Semiconductor will make the things. Tilera has previously said to expect prices ranging from $500 to $1,000.

It says the 8000 line will deliver 28 Gbps-80 Gbps of packet processing with its top end capable of 450 billion operations-a-second on a single processor. Each chip has an advanced virtual memory system and each core includes 32 kilobytes (kB) of L1 I-cache, 32 kB of L1 D-cache and 256 kB L2 cache, with up to 32 megabytes L3 coherent cache across the device.

Figure the 8016 for 15W, the 8032 25W, the 8064 40W and the 8100 55W.

Tilera says an on-chip Multistream iMesh Crypto Accelerator (MiCA) system delivers 20 Gbps-80 Gbps encryption and 20 Gbps full-duplex compression processing, tightly coupled to its proprietary iMesh architecture for low latency and wire-speed small packet throughput.

A high-performance true random number generator and public key accelerator reportedly enables up to 60,000 RSA handshakes a second.

The Gx 8000 also includes a so-called mPIPE (multi-core Programmable Intelligent Packet Engine) system for wire-speed packet classification, load balancing and buffer management. This C-programmable engine delivers 80 Gbps and 120 million packets-a-second of throughput for handling multiple layers of packet encapsulation.

Tilera recently raised a $45 million round although it was reportedly on the edge of profitability. At the time an IPO was penciled in for 2013 when it should be at 225 cores. Total investment comes to $109 million including strategic investments from Cisco and Samsung.

Separately, Tilera has added support for the Intel-owned Wind River Linux and Workbench tools to its Tile Gx and second-generation Tile Pro chips to help with migration of legacy designs.

More Stories By Maureen O'Gara

Maureen O'Gara the most read technology reporter for the past 20 years, is the Cloud Computing and Virtualization News Desk editor of SYS-CON Media. She is the publisher of famous "Billygrams" and the editor-in-chief of "Client/Server News" for more than a decade. One of the most respected technology reporters in the business, Maureen can be reached by email at maureen(at)sys-con.com or paperboy(at)g2news.com, and by phone at 516 759-7025. Twitter: @MaureenOGara

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